1. Field of the Invention
This invention relates to switching power supply controllers.
2. Description of the Related Art
Switching power supply controllers are typically fabricated as an integrated circuit (IC), which is connected to external components such as an output inductor and capacitor to form a complete switching power supply. A switching power supply requires one or more switching elements, which can be on- or off-chip.
A typical switching power supply configuration is shown in FIG. 1. The on-chip components include a switching transistor MP1 connected between an input voltage Vin and a switching node 10, and a switching transistor MN1 connected between switching node 10 and an internal chip ground node 12. An error amplifier A1 receives a feedback signal Vfbd which varies with the power supply's output voltage Vout (typically via a resistive divider 14) and a reference voltage Vref at respective inputs, and produces an output which drives the controller's switch driving circuitry 16, typically using pulse width modulation (PWM). When so arranged, both Vfbd and Vref are referred to internal chip ground node 12. External components such as output inductor L and output capacitor C are connected to the controller IC to complete the switching power supply. The controller operates to regulate output voltage Vout by controlling a ‘switching cycle’, which includes a first portion during which MP1 is closed and MN1 is open, and a second portion during which MP1 is open and MN1 is closed.
However, a problem can arise with a switching power supply controller IC having on-chip switches, such as that shown in FIG. 1. During the portion of the switching cycle when MN1 is turned on (and MP1 is off), all of the switch current isw flows through chip ground node 12. However, chip ground node 12 must be connected an external ground node 20, to which the external components are referred. Ideally, there would be no resistance between chip ground node 12 and external ground node 20. However, in practice, a parasitic resistance RP is present between these nodes. When switch current isw flows through RP, a voltage drop is developed across RP which can reduce the accuracy of feedback signal Vfbd. This inaccuracy does not affect the feedback signal during the portion of the switching cycle when MP1 is turned on (and MN1 is off), because during this period, the switch current flows through switching node 10 and into inductor L, rather than through RP. Thus, there is an error in the feedback signal only during certain portions of the switching cycle. Moreover, the parasitic resistance between the external ground node and the chip ground node is generally beyond the direct control of the controller designer, and so the magnitude of the resulting voltage drop is unknown.
One previous effort to address this problem involves the use of separate power and analog grounds to enable the controller to obtain an accurate measurement of the output voltage throughout the entire switching cycle. This approach, however, requires additional pins which are too costly for many applications. Another approach is to estimate the voltage drop caused by the switch current flowing through the parasitic resistance and to adjust the feedback accordingly. This approach, however, requires knowledge of the parasitic resistance value, which as mentioned above, is generally beyond the control of the designer.